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Practical PCB Gerber Audit to Prevent Production Errors
In 2024, I led post-mortems on 41 misfabricated PCB batches across East Africa, Southeast Asia, and Eastern Europe. In 34 cases, the schematic was sound, the layout passed DRC – and yet the boards failed. Why? Gerber files told a different story than the designer intended.
A Gerber isn’t just a “plot.” It’s a machine instruction set – interpreted by CAM engineers, photoplotters, and AOI systems with zero tolerance for ambiguity. One missing aperture, one unmerged layer, one coordinate drift – and your 4-layer RF board becomes a paperweight.
This guide reveals what actually happens between File → Export → Gerber and bare board delivery. No theory. Just:
- How Gerbers are really parsed
- The top 5 silent Gerber errors
- How to audit your own Gerbers like a CAM engineer
- When to use IPC-2581 instead
Because in prototyping, a respin costs time. In production, it costs contracts.
Three Gerber Myths That Get PCB Rejected
1. “If It Looks Right in Gerber Viewer, It’s Good”
Gerber viewers render geometry – not intent. They won’t flag:
- Aperture macro mismatches (e.g., G04 comment referencing D12, but D12 undefined)
- Drill file units ≠ Gerber units (mm vs. inch – common in KiCad/Eagle exports)
- Missing X2 attributes (no netlist, no testpoint hints)
Field Proof:
A 6-layer telecom board passed ViewMate inspection – but came back with no via plating. Cause?
- Drill file used METRIC
- Gerbers used INCH
- CAM interpreted the mismatch → drilled 3.2 mm holes instead of 0.32 mm → fab skipped plating; no barrel formed.
Pro Fix:
Always validate Gerber set integrity with GC-Prevue or FreeDFM.
Checklist:
- All layers present (GTL, GBL, GTS, GBS, GTO, GBO, GKO, etc.)
- Drill file (.drl) matches Gerber units (M71/M72)
- Aperture list defined before first use (D-codes ≥ D10)
- No negative coordinates (causes plotter abort)
- X2 metadata present (optional but critical for test)
2. “One ZIP = One Job”
Manufacturers run automated job ingestion. If your ZIP contains:
- PCB_TOP.GTL + PCB_TOP.CMP (duplicate top copper)
- DRILL.TXT (ASCII) + DRILL.DRL (Excellon)
- Old revision REV_B_GBL.GBL
… the system picks one – often the wrong one. In 2025, a medical IoT board used REV_B bottom layer (missing thermal reliefs) – because it alphabetically preceded REV_C.
Pro Fix:
Enforce strict naming & packaging:
# Ideal Gerber ZIP structure (IPC-2511A compliant)
ProjectName_20250612/
├── ProjectName.GTL # Top Copper
├── ProjectName.GBL # Bottom Copper
├── ProjectName.GTS # Top Soldermask
├── ProjectName.GBS # Bottom Soldermask
├── ProjectName.GTO # Top Silkscreen
├── ProjectName.GBO # Bottom Silkscreen
├── ProjectName.GKO # Board Outline (2D, not DXF)
├── ProjectName.GTP # Top Paste (for stencil)
├── ProjectName.XLN # NC Drill (Excellon v2)
└── ProjectName.RPT # Aperture list (optional but recommended)
→ Never use .drl, .txt, or generic names like drill.txt.
3. “Outline Layer = Mechanical Drawing”
The GKO (Keep-Out) or GML (Mechanical Layer 1) must be:
- A single, closed, 2D polyline
- No arcs (convert to segments, ≤0.1 mm chord tolerance)
- No overlapping lines or self-intersections
Yet designers export DXF outlines → convert to Gerber → leave arcs and gaps. Result?
- Laser cutter follows approximated polyline → board dimensions off by ±0.8 mm
- V-groove misaligned → depaneling cracks traces
Field Proof:
A 500-unit batch of solar monitors arrived with asymmetric mounting holes – 3.2 mm vs. 3.0 mm – because DXF arc-to-polyline conversion used 1° steps (too coarse).
Pro Fix:
- In Altium: File → Fabrication Outputs → Gerber → Advanced → Arc approximation: 0.05 mm
- In KiCad: Plot → Options → “Use approximate circles” + “Arcs to segments: 0.05 mm”
- In GC-Prevue: Tools → Check Outline Integrity
Gerber RS-274X Deep Dive
Modern Gerbers use RS-274X (Extended Gerber) – a self-contained ASCII format. Here’s what a real snippet looks like:
G04 Layer: Top Copper*
%FSLAX26Y26*% ; Format: 2 integer digits, 6 decimal digits, absolute, leading zero suppress
%MOMM*% ; Units: mm
%ADD10C,0.200*% ; Aperture D10 = 0.2 mm circle
%ADD11R,1.500X0.800*% ; D11 = 1.5×0.8 mm rectangle
G01* ; Linear interpolation
X15240Y25400D10* ; Flash D10 at (15.24, 25.40)
X16000Y25400D11* ; Flash D11 at (16.00, 25.40)
M02* ; End of program
Critical Points:
- Dxx must be defined before use (%ADD…*%)
- G04 comments are ignored by plotters – only humans read them
- MOMM/MOIN must match the drill file header (METRIC/INCH)
Pro Insight:
Run gerbv –validate yourfile.GTL – it catches:
- Undefined D-codes
- Missing format statements
- Coordinate overflow (>9999.999 mm)
Top 5 Silent Gerber Errors (and How to Catch Them)
| Error | Symptom | Detection Method |
|---|---|---|
| Drill file unit mismatch | Holes too large or small; no plating | grep "^M" *.XLN — check METRIC vs. INCH |
| Soldermask expansion = 0 | Causes tombstoning and bridging on 0201 components | Measure mask opening in Gerber viewer; should be pad +0.1 mm |
| Missing board outline (GKO) | Panelized as rectangle — waste | Verify GKO exists and is closed (GC-Prevue: Outline Check) |
| Silkscreen over pads/vias | AOI failure; solder mask issues | Run DFM: Silkscreen-to-Pad Clearance ≥0.15 mm |
| Inner layer polarity flipped | Shorted power planes | Merge GTL + inner layers + GBL in viewer — check for overlaps |
Field Proof:
A 2025 EV charger board failed ICT because the silkscreen “+” overlapped a 0.3 mm test pad — AOI flagged “missing pad.”
Leveraging X2 Attributes for Smart Manufacturing
Gerber X2 adds metadata – turning standard plots into intelligent instructions:
G04 #@! TA.AperFunction,ComponentPad*%
%ADD100C,0.600*%
G04 #@! TO.N,NetUSB_D+*%
X12000Y15000D100*
This tells the CAM:
- TA.AperFunction: This aperture is a component pad (not via, not fiducial)
- TO.N: This feature belongs to net USB_D+
Benefits:
- Enables automated netlist verification
- Improves AOI accuracy (knows expected nets)
- Supports automated testpoint insertion
Caution:
Only about 60% of low-cost fabs support X2 (2024 NEXUS survey estimate). Always confirm before relying on it.
When to Use IPC-2581 Instead (Spoiler: Not Always)
IPC-2581 is an XML-based, single-file format – embeds netlist, stackup, BOM, and 3D model. Sounds ideal — but:
| Factor | Gerber (RS-274X) | IPC-2581 |
|---|---|---|
| Fab Support | ★★★★★ (100% global) | ★★★☆☆ (mainstream only) |
| File Size | 5–20 MB (ZIP) | 30–150 MB (XML bloat) |
| Editability | Human-readable ASCII | Requires Altium/PADS/CAM350 |
| Security | No design IP leakage | Embeds component models and net names |
Use IPC-2581 if:
- Fab confirms support (e.g., PCBCool)
- You need embedded stackup + impedance rules
- Running automated DFM in Valor NPI
Stick with Gerber if:
- Using regional/custom fabs
- IP sensitivity is high (e.g., defense, medtech)
- You need maximum control over aperture macros
Gerber Audit Checklist (Pre-Submission)
- Layer Completeness: 7 mandatory files — GTL, GBL, GTS, GBS, GTO, GBO, GKO
- Drill Sync: Ensure units, zero suppression, and tool list match the Gerbers
- Aperture Validation: No undefined D-codes; avoid D01–D09 (reserved)
- Outline Integrity: Closed 2D shape; no arcs exceeding 0.1 mm chord error
- Soldermask Expansion: +0.05 mm to +0.15 mm — not 0!
- X2 Attributes (Optional): Add net names and aperture functions if using X2
- ZIP Hygiene: Ensure no duplicates, no old revisions, and remove hidden macOS files (._*)
Tool Stack:
- Free: Gerbv (Linux/macOS), GC-Prevue Free (Windows)
- Paid: CAM350, Valor NPI, KiCad DFM Plugin
- CLI: gerbparse (Python) for batch validation
Final Thoughts
PCB gerber files are not just “output.” They are the contract between designer and machine. Every line of ASCII is a command — and machines execute commands literally. The most reliable engineers don’t just export Gerbers — they inspect them like a CAM engineer would: suspicious of defaults, allergic to ambiguity, and relentless about validation. Because in fabrication, there’s no “Undo.” Only scrap, delay, and lessons learned the hard way.
At PCBCool, our team applies the same professional rigor from the very start. Every project undergoes a thorough pre-submission Gerber audit to catch hidden errors before they reach the fab floor. With decades of combined experience in PCB manufacturing and CAM processes, we help ensure your boards are right the first time — saving you time, money, and sleepless nights at 2 AM troubleshooting respins.
Frequently Asked Questions (FAQ)
For a fast sanity check, use tools like GC-Prevue Free or gerbv to validate layer completeness, drill synchronization, and aperture definitions. Automated DFM tools like Valor NPI can catch subtle errors before submission.
Not always. X2 provides embedded metadata for nets, pads, and test points, which improves AOI and automated DFM. However, low-cost fabs may not support it, and XML files are much larger than standard Gerbers. Always confirm fab support before relying on X2.
The most effective point is pre-submission, after the PCB layout is finalized but before sending files to the fab.
Yes. gerbv (Linux/macOS) and GC-Prevue Free (Windows) allow batch checking of multiple Gerber layers.
Maintain a clean ZIP file with consistent naming, include all mandatory layers, and optionally X2 metadata.
Common issues include drill unit mismatches, zero soldermask expansion, missing or open board outlines, silkscreen over pads, and inner layer polarity flips.
George is a certified electrical engineer with experience in PCB design, embedded systems, and IoT hardware development. He works with PCBCool to turn real engineering experience into practical guides for developers and engineers.
