{"id":43374,"date":"2026-03-23T14:14:30","date_gmt":"2026-03-23T06:14:30","guid":{"rendered":"https:\/\/pcbcool.com\/?p=43374"},"modified":"2026-03-23T14:29:58","modified_gmt":"2026-03-23T06:29:58","slug":"sbu-pcb-technology","status":"publish","type":"post","link":"https:\/\/pcbcool.com\/de\/technical-guides\/sbu-pcb-technology\/","title":{"rendered":"Sequentielle Aufbauherstellungstechnologie (SBU) in HDI-Leiterplatten"},"content":{"rendered":"
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Modern electronics continue to evolve toward higher performance, greater functionality, and smaller form factors. This trend places increasing demands on printed circuit board (PCB) design, where more complex circuits must be integrated into increasingly limited space.\u00a0Conventional multilayer PCB fabrication remains widely used, but it faces growing challenges in supporting ultra-fine routing, high interconnect density, and advanced packaging requirements.<\/span><\/p>

Sequential Build-Up (SBU) technology was introduced to address these challenges and has become a core process in High-Density Interconnect (HDI) PCB manufacturing. Unlike conventional methods that laminate multiple layers in a single cycle, SBU builds the PCB structure step by step by adding dielectric and copper layers sequentially onto a core substrate. This approach enables finer features, smaller vias, and significantly higher wiring density.<\/p>

However, the advantages of SBU come with increased process complexity. Each build-up stage involves multiple critical steps, including dielectric deposition, laser drilling (microvias), metallization, and plating. Variations at any stage can accumulate and affect overall yield and long-term reliability.<\/p>

Achieving stable manufacturing performance requires a deep understanding of process interactions, tight control of critical parameters, and effective strategies for managing variation across each build-up cycle.<\/p>

In this article, we focus on one of the most critical factors affecting SBU performance: microvia reliability and manufacturing yield stability. We will also introduce a practical framework to help engineers analyze root causes, control process variation, and improve overall yield and reliability in HDI PCB fabrication.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Why Sequential Build-Up Technology Is Used<\/h2> \n\t\t\t\t\t\t\t<\/div>\n\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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The growing adoption of Sequential Build-Up PCB technology is primarily driven by the increasing complexity of modern electronic systems.<\/p>

Advanced packaging technologies such as ball grid arrays (BGAs), chip-scale packages (CSPs), and flip-chip devices feature extremely fine pitches and dense I\/O configurations. Routing signals out from beneath these components\u2014commonly referred to as \u201cescape routing\u201d\u2014requires significantly higher interconnect density than what conventional multilayer PCB designs can efficiently support.<\/p>

Traditional multilayer PCB rely heavily on mechanically drilled through-holes. While robust and cost-effective, these vias occupy considerable space across all layers and can restrict routing channels. In addition, they introduce electrical challenges such as via stubs, larger parasitic capacitance and inductance, and impedance discontinuities, all of which can negatively impact signal integrity\u2014especially in high-speed designs.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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SBU technology addresses these limitations by enabling the use of laser-drilled microvias and sequential layer construction (e.g., 2+1+2 stack-ups). Microvias are much smaller than through-holes and can be placed more precisely, including directly in component pads (via-in-pad). This allows for more efficient escape routing and significantly improves routing density without increasing board size.<\/p>

From an electrical perspective, SBU also offers important advantages. By reducing via size, shortening interconnect paths, and minimizing parasitic effects, it helps improve signal integrity in high-speed, multi-gigahertz systems. This is particularly important for designs sensitive to signal reflections, impedance mismatches, and electromagnetic crosstalk.<\/p>

Finally, SBU enables a more optimized layer build-up strategy. Instead of laminating all layers at once, manufacturers can selectively add layers only where needed, which can improve design flexibility and, in some cases, enhance manufacturing efficiency.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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SBU PCB Manufacturing Process<\/h2> \n\t\t\t\t\t\t\t<\/div>\n\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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The defining feature of SBU PCB construction is its layer-by-layer fabrication approach. The typical manufacturing process can be described in the following steps:<\/p>

  1. Core Substrate Fabrication<\/em><\/li><\/ol>

    The process begins with the fabrication of a core substrate, which serves as the mechanical and electrical foundation of the PCB. This core may include one or more copper layers used for power distribution or signal routing. Standard photolithography and etching processes are used to define circuit patterns, and mechanical drilling is performed to create any required through-holes.<\/p>

    1. Dielectric Layer Lamination<\/em><\/li><\/ol>

      Once the core is completed, a thin dielectric layer is laminated onto its surface. This is typically achieved using resin-coated copper (RCC) or specialized prepreg materials. Compared to conventional multilayer boards, the dielectric used in SBU is significantly thinner, allowing tighter layer spacing.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

      \n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\"Schematic\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t
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      1. Laser Drilling of Microvias<\/em><\/li><\/ol>

        After lamination, microvias are formed using laser drilling. Unlike traditional through-holes, microvias typically connect only adjacent layers (blind vias) rather than passing through the entire board. Their small size\u2014commonly in the range of 50\u2013100 microns in diameter\u2014enables high interconnect density and precise routing in HDI designs.<\/span><\/p>

        1. Metallization and Copper Plating<\/em><\/li><\/ol>

          The drilled microvias are then metallized. This process begins with the deposition of a thin conductive seed layer (commonly via electroless copper deposition), followed by electroplating to build up sufficient copper thickness. In many designs, microvias are fully or partially copper-filled to create a flat, reliable surface for subsequent layers.<\/p>

          1. Pattern Formation<\/em><\/li><\/ol>

            Once the copper layer is established, photolithography and etching processes are used to define the circuit patterns on the newly added layer.<\/p>

            1. Sequential Layer Build-Up<\/em><\/li><\/ol>

              Steps 2 through 5 are repeated as needed to achieve the required number of build-up layers (e.g., 1+N+1<\/a>, 2+N+2 structures<\/a>). Each cycle adds additional routing capability and interconnect density, allowing the PCB to meet increasingly complex design requirements.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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              Microvia Defects in SBU PCB<\/h2> \n\t\t\t\t\t\t\t<\/div>\n\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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              As discussed previously, microvias are formed after each build-up layer is laminated and are typically very small in size. In multi-layer sequential lamination structures, microvias can be arranged in two primary configurations: stacked (vertically aligned) or staggered (offset between layers).<\/p>

              Stacked microvias offer clear advantages in terms of space utilization and routing efficiency, especially in high-density designs. However, they also introduce greater reliability risks compared to staggered structures, particularly under thermal and mechanical stress. As a result, stacked microvias are often considered one of the most critical challenges in SBU PCB manufacturing.<\/p>

              During production, manufacturers may encounter several types of microvia-related defects:<\/p>